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Nmos And Pmos Comparison Essay

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Difference Between NMOS and PMOS

Difference Between NMOS and PMOS

A FET (Field Effect Transistor) is a voltage controlled device where its current carrying ability is changed by applying an electronic field. A commonly used type of FET is the Metal Oxide Semiconductor FET (MOSFET). MOSFET are widely used in integrated circuits and high speed switching applications. MOSFET work by inducing a conducting channel between two contacts called the source and the drain by applying a voltage on the oxide-insulated gate electrode. There are two main types of MOSFET called nMOSFET (commonly known as NMOS) and pMOSFET (commonly known as PMOS) depending on the type of carriers flowing through the channel.

As mentioned earlier, NMOS (nMOSFET) is a type of MOSFET. A NMOS transistor is made up of n-type source and drain and a p-type substrate. When a voltage is applied to the gate, holes in the body (p-type substrate) are driven away from the gate. This allows forming an n-type channel between the source and the drain and a current is carried by electrons from source to the drain through an induced n-type channel. Logic gates and other digital devices implemented using NMOSs are said to have NMOS logic. There are three modes of operation in a NMOS called the cut-off, triode and saturation. NMOS logic is easy to design and manufacture. But circuits with NMOS logic gates dissipate static power when the circuit is idling, since DC current flows through the logic gate when the output is low.

As mentioned earlier, PMOS (pMOSFET) is a type of MOSFET. A PMOS transistor is made up of p-type source and drain and a n-type substrate. When a positive voltage is applied between the source and the gate (negative voltage between gate and source), a p-type channel is formed between the source and the drain with opposite polarities. A current is carried by holes from source to the drain through an induced p-type channel. A high voltage on the gate will cause a PMOS not to conduct, while a low voltage on the gate will cause it to conduct. Logic gates and other digital devices implemented using PMOS are said have PMOS logic. PMOS technology is low cost and has a good noise immunity.

What is the difference between NMOS and PMOS?

NMOS is built with n-type source and drain and a p-type substrate, while PMOS is built with p-type source and drain and a n-type substrate. In a NMOS, carriers are electrons, while in a PMOS, carriers are holes. When a high voltage is applied to the gate, NMOS will conduct, while PMOS will not. Furthermore, when a low voltage is applied in the gate, NMOS will not conduct and PMOS will conduct. NMOS are considered to be faster than PMOS, since the carriers in NMOS, which are electrons, travel twice as fast as holes, which are the carriers in PMOS. But PMOS devices are more immune to noise than NMOS devices. Furthermore, NMOS ICs would be smaller than PMOS ICs (that give the same functionality), since the NMOS can provide one-half of the impedance provided by a PMOS (which has the same geometry and operating conditions).

Other articles

How do I treat a PMOS compared to an NMOS in small-signal analysis? Electrical Engineering Stack Exchange

What exhaustive list can I use to determine the differences between NMOS and PMOS devices when doing small-signal analysis?

Equivalently, what are the fundamental differences between NMOS and PMOS devices, and how do related terms (i.e. treshold voltage, which is either positive in NMOS and negative in PMOS, or positive in both but with reversed polarity in PMOS, affecting many formulas) differ between them?

asked May 28 '12 at 22:23

The only real difference is in the mobility of the carriers, where electrons are faster than holes (around 2x) thus giving nMOS transistor a 2 times better performance for everything else equal.

About notation, it's mostly a practical thing, and the small signal model is an abstraction that you make to analyze a circuit. So you can use it the way you understand it better.

For instance, I usually use magnitudes (flipping notations drives me crazy) and then determine the direction of the current and voltage from the circuit. So the nMOS will generally have a current from drain to source, and the pMOS from source to drain, both with positive sign.

pMOS's \$I_ \$ will be proportional to \$V_ - |V_T| \$, where nMOS's \$I_ \$ will be proportional to \$V_ - |V_T| \$. Note that for the pMOS, you can flip SG and SD and still obtain the right values, as long as you use the absolute value of Vt.

answered May 29 '12 at 9:24

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Computer Electronics

1 NMOS and CMOS Logic Gates 1.1 Transistor Switches

Logic circuits are built with transistors. For the purpose of understanding how logic circuits are built, we can assume that a transistor operates as a simple switch. Figure 1a shows a switch controlled by a logic signal, x. When x is low, the switch is open, and when x is high, the switch is closed. The most popular type of transistor for implementing a simple switch is the metal oxide semiconductor field-effect transistor (MOSFET). There are two different types of MOSFETs, known as n-channel. abbreviated NMOS . and p-channel. denoted PMOS .

Figure 1b gives a graphical symbol for an NMOS transistor. It has four electrical terminals, called the source. drain. gate. and substrate. In logic circuits the substrate (also called body ) terminal is connected to Gnd. We will use the simplified graphical symbol in Figure 1c. which omits the substrate node. There is no physical difference between the source and drain terminals. They are distinguished in practice by the voltage levels applied to the transistor; by convention, the terminal with the lower voltage level is deemed to be the source.

(a) A simple switch controlled by the input x

(b) NMOS transistor

(c) Simplified symbol for an NMOS transistor

Figure 1 NMOS transistor as a switch

It is controlled by the voltage VG at the gate terminal. If VG is low, then there is no connection between the source and drain, and we say that the transistor is turned off. If VG is high, then the transistor is turned on and acts as a closed switch that connects the source and drain terminals.

PMOS transistors have the opposite behavior of NMOS transistors. The former are used to realize the type of switch illustrated in Figure 2a. where the switch is open when the control input x is high and closed when x is low. A symbol is shown in Figure 2b. In logic circuits the substrate of the PMOS transistor is always connected to VDD . leading to the simplified symbol in Figure 2c. If VG is high, then the PMOS transistor is turned off and acts like an open switch. When VG is low, the transistor is turned on and acts as a closed switch that connects the source and drain. In the PMOS transistor the source is the node with the higher voltage.

(a) A switch with the opposite behavior of Figure 1a

(b) PMOS transistor

(c) Simplified symbol for an PMOS transistor

Figure 2 PMOS transistor as a switch.

(a) NMOS transistor

(b) PMOS transistor

Figure 3 NMOS and PMOS transistors in logic circuits

Figure 3 summarizes the typical use of NMOS and PMOS transistors in logic circuits. An NMOS transistor is turned on when its gate terminal is high, while a PMOS transistor is turned on when its gate is low. When the NMOS transistor is turned on, its drain is pulled down to Gnd. and when the PMOS transistor is turned on, its drain is pulled up to VDD . Because of the way the transistors operate, an NMOS transistor cannot be used to pull its drain terminal completely up to VDD . Similarly, a PMOS transistor cannot be used to pull its drain terminal completely down to Gnd .

1.2 NMOS Logic Gates

The first schemes for building logic gates with MOSFETs became popular in the 1970s and relied on either PMOS or NMOS transistors, but not both. Since the early 1980s, a combination of both NMOS and PMOS transistors has been used. We will first describe how logic circuits can be built using NMOS transistors because these circuits are easier to understand. Such circuits are known as NMOS circuits. Then we will show how NMOS and PMOS transistors are combined in the presently popular technology known as complementary MOS. or CMOS .

In the circuit in Figure 4a. when Vx = 0 V, the NMOS transistor is turned off. No current flows through the resistor R. and Vf = 5 V. On the other hand, when Vx = 5V, the transistor is turned on and pulls Vf to a low voltage level. The exact voltage level of Vf in this case depends on the amount of current that flows through the resistor and transistor. Typically, Vf � is about 0.2V. If Vf is viewed as a function of Vx . then the circuit is an NMOS implementation of a NOT gate. In logic terms this circuit implements the function f = x .

The purpose of the resistor in the NOT gate circuit is to limit the amount of current that flows when Vx = 5V. Rather than using a resistor for this purpose, a transistor is normally used. In subsequent diagrams a dashed box is drawn around the resistor R as a reminder that it is implemented using a transistor.

Figure 4b presents the graphical symbols for a NOT gate. The left symbol shows the input, output, power, and ground terminals, and the right symbol is simplified to show only the input and output terminals. In practice only the simplified symbol is used. Another name often used for the NOT gate is inverter .

(a) Circuit diagram

(b) Graphical symbols

Figure 4 A NOT gate built using NMOS technology.

Using NMOS transistors, we can implement the series connection as depicted in Figure 5a. If Vx1 = Vx2 = 5V, both transistors will be on and Vf will be close to 0V. But if either Vx1 or Vx2 is 0, then no current will flow through the series-connected transistors and Vf will be pulled up to 5V. The resulting truth table for f. provided in terms of logic values, is given in Figure 5a. The realized function is the complement of the AND function, called the NAND function, for NOT-AND. The circuit realizes a NAND gate. Its graphical symbols are shown in Figure 5b.

The parallel connection of NMOS transistors is given in Figure 6a. Here, if either Vx1 = 5V or Vx2 = 5V, then Vf will be close to 0 V. Only if both Vx1 and Vx2 are 0 will Vf be pulled up to 5V. A corresponding truth table is given in Figure 6a. It shows that the circuit realizes the complement of the OR function, called the NOR function, for NOT-OR. The graphical symbols for the NOR gate appear in Figure 6b.

(b) Graphical symbols

Figure 5 NMOS realization of a NAND gate

(b) Graphical symbols

Figure 6 NMOS realization of a NOR gate

Instead of the NAND and NOR gates just described, the reader would naturally be interested in the AND and OR gates that were used extensively in the previous chapter. Figure 7 indicates how an AND gate is built in NMOS technology by following a NAND gate with an inverter. Node A realizes the NAND of inputs x1 and x2. and f represents the AND function. In a similar fashion an OR gate is realized as a NOR gate followed by an inverter, as depicted in Figure 8.

(b) Graphical symbols

Figure 7 NMOS realization of an AND gate

(b) Graphical symbols

Figure 8 NMOS realization of an OR gate

1.3 CMOS Logic Gates

So far we have considered how to implement logic gates using NMOS transistors. For each of the circuits that has been presented, it is possible to derive an equivalent circuit that uses PMOS transistors. However, it is more interesting to consider how both NMOS and PMOS transistors can be used together. The most popular such approach is known as CMOS technology. CMOS technology offers some attractive practical advantages in comparison to NMOS technology.

In NMOS circuits the logic functions are realized by arrangements of NMOS transistors, combined with a pull-up device that acts as a resistor. We will refer to the part of the circuit that involves NMOS transistors as the pull-down network (PDN). Then the structure of the circuits in Figures 4 through 8 can be characterized by the block diagram in Figure 9. The concept of CMOS circuits is based on replacing the pull-up device with a pull-up network (PUN) that is built using PMOS transistors, such that the functions realized by the PDN and PUN networks are complements of each other. Then a logic circuit, such as a typical logic gate. is implemented as indicated in Figure 10. For any given valuation of the input signals, either the PDN pulls Vf down to Gnd or the PUN pulls Vf up to VDD . The PDN and the PUN have equal numbers of transistors, which are arranged so that the two networks are duals of one another. Wherever the PDN has NMOS transistors in series, the PUN has PMOS transistors in parallel, and vice versa.

The simplest example of a CMOS circuit, a NOT gate, is shown in Figure 11. When Vx = 0V, transistor T2 is off and transistor T1 is on. This makes Vf = 5V, and since T2 is off, no current flows through the transistors. When Vx = 5V, T2 is on and T1 is off. Thus Vf = 0V, and no current flows because T1 is off.

A key point is that no current flows in a CMOS inverter when the input is either low or high. This is true for all CMOS circuits; no current flows, and hence no power is dissipated under steady state conditions. This property has led to CMOS becoming the most popular technology in use today for building logic circuits.

Figure 12 provides a circuit diagram of a CMOS NAND gate. It is similar to the NMOS circuit presented in Figure 5 except that the pull-up device has been replaced by the PUN with two PMOS transistors connected in parallel. The truth table in the figure specifies the state of each of the four transistors for each logic valuation of inputs x1 and x2. The reader can verify that the circuit properly implements the NAND function. Under static conditions no path exists for current flow from VDD to Gnd .

The circuit in Figure 12 can be derived from the logic expression that defines the NAND operation, . This expression specifies the conditions for which f = 1; hence it defines the PUN. Since the PUN consists of PMOS transistors, which are turned on when their control (gate) inputs are set to 0, an input variable xi turns on a transistor if xi = 0. From DeMorgan�s law, we have

Figure 9 Structure of an NMOS circuit.

Thus f = 1 when either input x1 or x2 has the value 0, which means that the PUN must have two PMOS transistors connected in parallel. The PDN must implement the complement of f. which is

Figure 10 Structure of a CMOS circuit

Figure 11 CMOS realization of a NOT gate

Since f = 1 when both x1 and x2 are 1, it follows that the PDN must have two NMOS transistors connected in series.

The circuit for a CMOS NOR gate is derived from the logic expression that defines the NOR operation

Since f = 1 only if both x1 and x2 have the value 0, then the PUN consists of two PMOS transistors connected in series. The PDN, which realizes f = x1 + x2. has two NMOS transistors in parallel, leading to the circuit shown in Figure 13.

Figure 12 CMOS realization of a NAND gate

Figure 13 CMOS realization of a NOR gate

A CMOS AND gate is built by connecting a NAND gate to an inverter, as illustrated in Figure 14. Similarly, an OR gate is constructed with a NOR gate followed by a NOT gate.

The above procedure for deriving a CMOS circuit can be applied to more general logic functions to create complex gates. This process is illustrated in the following two examples.

Figure 14 CMOS realization of an AND gate

Difference Between NMOS and PMOS

Difference Between NMOS and PMOS Main Difference –NMOS vs. PMOS

NMOS and PMOS are two different types of MOSFETs. The main difference between NMOS and PMOS is that, in NMOS, the source and the drain terminals are made of n- type semiconductors whereas, in PMOS, the source and the drain are made of p- type semiconductors .

What is MOSFET

A MOSFET is a type of unipolar transistor used in electronics. MOSFET stands for “Metal Oxide Semiconductor Field Effect Transistor “. Essentially, in a MOSFET, the current flow from one terminal to the other (the source and the drain) is determined by the voltage applied to a “gate” terminal. The current flows within the region called the “bulk” region. How a MOSFET works is explained in this article. Depending on which type of semiconductor makes up the different terminals, MOSFETS are classified into NMOS and PMOS.

What is NMOS

In NMOS devices, the source and the drain are made from n -type semiconductors while the bulk is made of p -type semiconductors. When the gate is given a positive voltage, holes between the two n -type regions get repelled and allow for electrons to flow between the source and the drain. The diagram below shows the structure of a MOSFET.

The structure of an NMOS MOSFET

The majority carriers in NMOS devices are electrons, and they can flow much faster than holes. As a result, NMOS transistors are smaller than corresponding PMOS devices. Consequently, NMOS are cheaper to produce than PMOS as well. Since electrons are faster than holes, NMOSs are also more useful in fast-switching applications. For instance, NMOS had been used for logic gates, although nowadays they have been largely replaced by “CMOSs” which contain a combination of NMOS and PMOS.

Most of the contaminants in MOSFETs are positively-charged. This gives a disadvantage to NMOS s because the accumulation of these contaminants around the gate could turn an NMOS device on when it is supposed to be off.

What is PMOS

In PMOS devices, the source and the drain are made of p- type material while the bulk is made of n type semiconductors. When a negative voltage is applied to the gate, the electrons get repelled and so holes are able to form a channel and travel between the source and the drain. In PMOS, the majority carriers are holes. Holes flow much more slowly compared to electrons, therefore it is much easier to control the current.

Difference Between NMOS and PMOS Fabrication:

In NMOS. the source and the drain are made of n- type semiconductors while the bulk is made of a p- type semiconductor.

In PMOS. the source and the drain are made of p- type semiconductors while the bulk is made of an n- type semiconductor.

Majority Carriers:

In NMOS. the majority carriers are electrons.

In PMOS. the majority carriers are holes.


NMOS devices are comparatively smaller compared with PMOS devices with complimentary conducting properties.

Operating Speed:

NMOS devices can be switched faster compared to PMOS devices.

Nmos and pmos comparison essay

Author to whom correspondence should be addressed; Email: Tel. +1-617-627-5113; Fax: +1-617-627-3220.

Received: 15 March 2012; in revised form: 8 May 2012 / Accepted: 8 May 2012 / Published: 18 May 2012


: We present a low voltage, low power operational transconductance amplifier (OTA) designed using a Fully Depleted Silicon-on-Insulator (FDSOI) process. For very low voltage application down to 0.5 V, two-stage miller-compensated OTAs with both p-channel MOSFET (PMOS) and n-channel MOSFET (NMOS) differential input have been investigated in a FDSOI complementary metal oxide semiconductor (CMOS) 150 nm process, using 0.5 V threshold transistors. Both differential input OTAs have been designed to operate from the standard 1.5 V down to 0.5 V with appropriate trade-offs in gain and bandwidth. The NMOS input OTA has a simulated gain/3 dB-bandwidth/power metric of 9.6 dB/39.6 KHz/0.48 µW at 0.6 V and 46.6 dB/45.01 KHz/10.8 µW at 1.5 V. The PMOS input OTA has a simulated metric of 19.7 dB/18.3 KHz/0.42 µW at 0.4 V and 53 dB/1.4 KHz/1.6 µW at 1.5 V with a bias current of 125 nA. The fabricated OTAs have been tested and verified with unity-gain configuration down to a 0.5 V supply voltage. Comparison with bulk process, namely the IBM 180 nm node is provided and with relevant discussion on the use of FDSOI process for low voltage analog design.

sub-threshold; weak inversion; analog design; OTA; low power; FDSOI

1. Introduction

The growth in the area of portable biosensors, handheld wireless devices and implanted medical devices has created more interest in low power circuits [1 ]. Advances in CMOS technology have allowed for lower dynamic power dissipation, higher speed of operation, higher density and many other advantages. Silicon-On-Insulator (SOI) technology is being proposed as the next node in the design of low power digital Very Large Scale Integration (VLSI) circuits. This technology allows for further decrease in power and thus heat dissipation by, first, extending the trend in minimizing the voltage supply and, second, by reducing the capacitance; as the insulated localized “body” reduces the capacitance and thus minimizes the required charge to create the channel. These two benefits lower the dynamic power, which for digital circuits is approximately proportional to CV 2 f, where C is the sum total of all the capacitances in the circuit, V is the power supply, and f is the frequency of operation. We also expect that these benefits will carry over to analog circuits if appropriate analog-favorable options such as high transconductance, higher output impedance, etc. can be provided in these processes; thus eventually allowing one to achieve a mixed-signal system on chip (SoC) solutions.

Whereas the devices in the standard bulk CMOS process are fabricated on the silicon bulk/substrate, the devices in the SOI are fabricated on a thinner silicon layer, which is separated from the bulk by an insulation layer. The main advantage will be the reduced capacitance, hence increased speed, and reduced coupling or interference through the substrate that reduces overall noise. Low power amplifiers in standard SOI processes have been demonstrated in previous studies [2 ,3 ]. The SOI process comes in two types: the partially depleted SOI (PDSOI) process and the fully depleted SOI (FDSOI) process.

In FDSOI, the top silicon layer is much thinner than in PDSOI (<100 nm vs. >100 nm). The PDSOI process also exhibits a floating body effect, as the region under the channel is partially depleted of charges, leading to some charge accumulation. Since the body is not connected to any potential, the accumulated charge alters the threshold voltage of the devices and could result in transistors exhibiting large threshold voltage variation within the same die. In FDSOI, the thinness of the silicon under the channels results in full depletion and no charge accumulation, and while the body is still floating, the effect on the threshold voltages of the transistor is uniform across the die. This makes FDSOI an ideal choice for analog circuitry where process variations can result in high offsets or common mode noise.

Both processes have been optimized and brought to market for digital designs. In such designs, where one cares merely whether the switch is turned on or off, the floating body or a kink effect in such SOI processes causes only minor degradation, such as a shift in threshold voltage. This may limit the speed of operation of the device by affecting the delay of the logic cell and may affect the noise margin [4 ]. However simple design approaches suffice to mitigate such issues in digital applications. In analog design such shifts may result in non-linearity effects, noise degradation and dynamic range especially in low voltage implementations where voltage headroom is not sufficient.

FDSOI is now also an analog compatible process as diodes, capacitors and resistors are part of the available technology. Given that not much has been studied in terms of analog design, we are planning on studying basic analog blocks in such a process. Furthermore, these processes are being optimized for very low supply voltages for both digital and analog circuitry. Low power applications such as biomedical implantable devices and others applications require high energy efficiency and operating the transistors in saturation region is not too favorable. Sub-threshold region or weak inversion region provides the best option for the highest energy efficiency when the frequency or bandwidth is not an important requirement [5 ].

Besides the benefits of supply voltage and thus power reduction in weak inversion operation, sub-threshold operation can also provide the highest transconductance ( gm ) for a given drain current [6 ]. For the chosen process, as well as the IBM 180 nm node, we observe a high number of gm / Id in weak inversion, as shown in Figure 1. The IBM 180 nm process was chosen as this technology has already been validated for analog design in the sub-threshold operation with conventional bulk devices [7 ]. Given the benefits of sub-threshold operation, our focus in this paper is on verifying its suitability in realizing a two stage operational amplifiers with ultra-low power of less than 0.5 µW in a sub-threshold region optimized 150 nm FDSOI CMOS digital process.

Figure 1. gm / Id curve of PMOS and NMOS devices for MITLL 150 nm FDSOI and IBM CMOS 180 nm.

Figure 1. gm / Id curve of PMOS and NMOS devices for MITLL 150 nm FDSOI and IBM CMOS 180 nm.

2. Analysis and Simulation Results 2.1. FDSOI vs. PDSOI vs. Bulk Process

Analog design has been proven robust in standard digital bulk processes for decades, but as the technology migrates to Partially Depleted Silicon-on-Insulator (PDSOI) and then onto FDSOI, an investigation of the merits of FDSOI for analog amplifiers is timely. The merits of the technology are many, from the proven shrinking of the CMOS device, the lower leakage current, less short channel effects (SCE), lower expected Vth variations due to lower dopant fluctuations, lower voltage supply and thus lower expected power consumptions. Figure 2 below displays the comparison between bulk PDSOI and FDSOI.

Figure 2. Comparison between bulk PDSOI and FDSOI silicon processes [8 ].

Figure 2. Comparison between bulk PDSOI and FDSOI silicon processes [8 ].

When compared to the PDSOI technology, the FDSOI process is free of the floating body effect and has higher immunity to the kink effect. The kink effect which is due to impact ionization can be observed when a discontinuity occurs in the Ids vs. Vds curve for higher Vds voltages in strong inversion, where the current increases at a faster rate beyond a certain Vds [4 ]. This is due to an increase in the body potential, and hence it is more prevalent in PDSOI than in FDSOI. The kink effect needs to be considered in analog design as it may contribute to device Vth mismatch. With SOI, smaller junction capacitance results in lower leakage current, due to less junction area and the non-existence of a leakage path to the substrate as the bulk is separated from the device by an oxide layer. Steep sub-threshold slope for high gain (and energy efficiency) may therefore be achieved in the FDSOI process which is impossible in the standard bulk process due to the inherent body effect.

Simulation results were carried out to evaluate the benefit of the MITLL FDSOI XLP 150 nm node process when compared to IBM’s Bulk process at the 180 nm node. The threshold voltages were found to be 0.22 V for the NMOS and 0.27 V for the PMOS in the bulk IBM 180 nm process and approximately 0.45 V–0.5 V in the FDSOI process. This digital process was of interest as, not only was it capable of ultra-low power operation, but it came with available resistors and capacitors that made the biasing and compensation of analog cells possible. The process also claimed an “anomalously steep sub-threshold slope” [9 ] and the kink effect was only present above a Vds of 1.1 V. Keeping devices below that bias voltage could thus minimize any kink effects. The sub-threshold slope and the gm / Id ratios were compared for both PMOS and NMOS devices. Both NMOS and PMOS device used have a width of 5 µm and a length of 1 µm. Minimum lengths were avoided to mitigate some short channel effects and because core analog blocks rarely rely on minimum length for matching purposes. From Figure 1. the gm / Id of the FDSOI process is maximized for weak inversion with a max ratio of approx. 42; which is much higher than in the strong inversion region where the gm / Id varies between 1 and 10 ( Vgs − Vth > 0.1 V). When comparing to IBM’s 180 nm bulk CMOS process, the gm / Id ratio for very low Id is 28 for the NMOS and 32 for the PMOS. As displayed in Figure 1. the FDSOI process proves to be superior at very low Id for both MOS devices that makes it an excellent choice for very low power application.

The sub-threshold slope factor is a significant parameter for the weak inversion operation of a device in the intended V range of operation. Its theoretical lower limit is 60 mV/dec, the slope factor S can be obtained in the following way [10 ]:

At very low Vgs of 0.25 V, the slope of the FDSOI process is 50 mV/dev for the NMOS and 52 mV/dev for the PMOS device. For the Bulk process, it is found to be 82 mV/dev for both of the NMOS and the PMOS device. Figure 3 displays the logarithmic drain current versus Vgs. displaying that the FDSOI process can provide a superior sub-threshold slope to the 180 nm bulk process at a supply voltage of 0.5 V. As such the FDSOI process was the right choice to investigate sub-threshold analog design.

Figure 3. Sub-threshold slope of FDSOI and Bulk CMOS devices (VDD = 0.5 V).

Figure 3. Sub-threshold slope of FDSOI and Bulk CMOS devices (VDD = 0.5 V).

Other advantages of the FDSOI process include reduced crosstalk, elimination of latch-up hazards, better transistor isolation (e.g. noise immunity), lower junction capacitance, and lower source-drain leakage [6 ]. These are all due to the reduced coupling to the substrate, as in effect all the devices are isolated from the bulk; and the n-type and p-types devices are more isolated from each other.

The main disadvantages of the FDSOI process when compared to the bulk are the higher costs, which would come down as the process becomes mainstream, the VT sensitivity to the silicon thickness, the higher series resistor and the floating body effects [6 ]. It is however important to realize that, as with any new technology, the total cost of production comes down once the technology becomes mainstream and is being mass produced.

2.2. Design of Two-Stage Differential Pair OTAs

In this paper, our goal was to utilize this advanced FDSOI process to realize a complete operational transconductance amplifier with both PMOS and NMOS input transistors and explore the possibility of aggressively scaling its supply voltage. A PMOS differential pair as well as a NMOS differential pair, as shown in Figure 4 and Figure 5. respectively, were designed and optimized to work in the sub-threshold region as well as in strong inversion. Simulation results point to a nominal threshold voltage of approximately 0.45 V–0.5 V for the chosen device sizes. Both designs are two-stage Miller compensated OTAs designed to operate over a 0.5 V–1.5 V range. The PMOS design has its bias current generated off chip, for fine tuning of the device on the bench for optimal operation. Its PMOS differential pair as well as the NMOS load devices use a length of 500 nm, guaranteeing a minimum of matching (proportional to ), while minimizing the voltage of operation. The NMOS design has its bias current generated on chip with a 1 MΩ resistor to GND. Its bias is set to (VDD−VGS)/ Rb for the chosen VDD. The NMOS differential pair uses a length of 450 nm and the PMOS load devices use a length of 300 nm.

Figure 4. PMOS input differential Amplifier.

Figure 4. PMOS input differential Amplifier.

Figure 5. NMOS input differential Amplifier.

Figure 5. NMOS input differential Amplifier.

Although the minimal length for this technology is 150 nm, no devices in either amplifier used a length of less than 300 nm. This reduces channel length modulation and increases output impedance. Moreover it provides better matching (process variation is inversely proportional to the area) and minimizes short channel artifacts such as leakage and second order VT dependencies. Only the ESD protections structure at each pin—off PMOS diode to VDD and off NMOS diode to GND—use the minimum length of 150 nm expecting these would turn on first during an ESD event. The equations of intrinsic parameters for a device in sub-threshold region with sufficient drain-source bias are as follow:

Leading to the gain of the OTAs to be the following [11 ]:

Since the amplifiers presented here are differential pairs, in layout all the transistors have their source local-body tied to eliminate any potential floating body effects and to ensure better matching, linearity and more stable VT over voltage [12 ], thus minimizing the disadvantages of the FDSOI process from an analog design standpoint. However, we expect that even if such source–body connections were not made, that such metrics would be better than in a PDSOI process. Since these were designed to operate at ultra-low power, self-heating and temperature concerns were not important. Furthermore the kink effects are usually observed at voltages above 1 V, thus the risk of kink effect can be omitted as devices were operating below the voltage of concern and were optimized to work in sub-threshold. In essence, the technology seemed ideal for ultra-low voltage and low power operation.

2.3. Simulation Results

Both OTAs were simulated with Spectre in a Cadence environment using BSIMSOI models with various supplies for various biasing conditions. Bias current is 125 nA for PMOS differential pair OTA. Table 1 and Table 2 summarize the various operating conditions. AC responses are presented in Figure 6 and transient results in Figure 7. All simulations were carried with 1 pF load.

Table 1. PMOS differential pair OTA simulation results.

It can be observed that in both designs, the gain decreases with a decreasing supply voltage, falling drastically when the devices run out of headroom and even below the sub-threshold saturation ( VDS < 3 KT/ q

75 mV). It is also worth pointing out that for the NMOS design where the current is controlled off chip; as expected, the gain is higher for a lower current as the devices are biased further in the weak inversion region. For the lowest specified voltage and current bias, the amplifiers can reach an ultra-low power of 0.5 µW; however, the gain is relatively low in the 10 dB range. With a higher current, the gain increases to 46.6 dB for the NMOS pair amplifier and 55.8 dB for the PMOS differential pair. The results are comparable with prior work [2 ,3 ,13 ]. In a standard SOI process, an OTA gain of 44 dB was achieved for a power of 3.6 µW when the supply was 1.2 V [2 ], while in another FDSOI 180 nm implementation an OTA with a gain of 64.5 dB when the supplies were ±0.75 V for a current draw of 472 µA and a power dissipation of 708 µW was designed [13 ]. What is unique in this paper is that the results show that similar performance can also be achieved in a fully depleted process with potential for even lower power consumption due to better sub-threshold slope.

Neither amplifier was optimized for minimal noise contribution, as the primary goal was to drive the OTAs in deep sub-threshold while consuming ultra-low power. Noise optimization is left for a future exercise. In both designs, the main contribution of noise was flicker noise as the differential amplifier pairs are small: W/L (NMOS_OTA) = 9 µm/450 nm and W/L (PMOS_OTA) = 10 µm/500 nm. For a Supply voltage (VDD) of 1.5 V and a common voltage (Vcm ) of 0.75 V, the input referred noise for the PMOS OTA is 89.33 nV/sqrt(Hz) for a bias current of 1 µA and it is 167.2 nV/sqrt(Hz) for a bias current of 125 nA. For a VDD of 0.5 V and a Vcm of 0.15 V, the input referred noise for the PMOS OTA is 99.4 nV/sqrt(Hz) for a bias current of 1uA and it is 163.3 nV/sqrt(Hz) for a bias current of 125 nA. For a VDD of 1.5 V and a Vcm of 0.75 V, the input referred noise for the NMOS OTA is 87.13 nV/sqrt(Hz) and it is 213.7 nV/sqrt(Hz) for a VDD of 0.6 V and a cm of 0.3 V. Noise results are reported at 10 kHz.

Figure 6. AC response (a ) PMOS differential pair for VDD = 0.4 V, CM = 0.15 V, I bias = 125 nA; (b ) NMOS diff pair, VDD = 0.6 V, CM = 0.3 V.

Figure 6. AC response (a ) PMOS differential pair for VDD = 0.4 V, CM = 0.15 V, I bias = 125 nA; (b ) NMOS diff pair, VDD = 0.6 V, CM = 0.3 V.

Figure 7. Transient response (a ) PMOS amplifier; (b ) NMOS amplifier in unity gain configuration.

Figure 7. Transient response (a ) PMOS amplifier; (b ) NMOS amplifier in unity gain configuration.

3. Experimental Results

Both amplifiers were fabricated on a chip in the MITLL XLP FDSOI 150 nm node. The microphotograph of the fabricated chip is displayed in Figure 8. All the pins for both amplifiers were brought out to pads, allowing for possible post processing, as well as for creating multiple configurations in the lab.

Figure 10 (a) below displays transient results for the PMOS differential pair in unity gain configuration as in Figure 9. while Figure 10 (b) displays the transient step response for the NMOS differential amplifier. The observed currents are much higher than anticipated and the output becomes noisy when the supply is lowered. Both amplifiers work down to 0.6 V in the lab, offset error seems to be the cause of lower supply performance. The PMOS differential pair is being monitored by setting the bias current on the bench but working biasing currents are much higher than simulation results predict. As such it could be expected that a floating body could only further deteriorate the matching, this experiment is left for a future work. Other work in the FDSOI process have demonstrated the performance of an RF amplifier not to be degraded for lower VDD supplies when the body is left floating [14 ], but here the matching of the differential pairs is of primary concern. Both devices rely on capacitors for their compensation, the NMOS diff pair also relied on resistors for compensation and current generation. From the early results, it can be inferred that the capacitors and resistors worked well and suggests that the MITLL 150 nm SOI process is an analog design compatible process. The observed offset and poor yield of functional devices led us to conclude that much needs to be done to optimize this process for predictable and stable analog operation.

Figure 8. Microphotograph of the entire chip (2 mm × 2 mm).

Figure 8. Microphotograph of the entire chip (2 mm × 2 mm).